The technical field is memory devices for storing data. More particularly, the technical field is memory devices having memory cells with tunnel junctions in series.
Memory devices are utilized in consumer electronic products to store data such as instructions utilized by the products. Nonvolatile memory devices are desirable because they do not require power to retain data. Therefore, data stored in nonvolatile memory devices is preserved when a power supply is exhausted or disconnected from the memory device. Consumers also prefer products of small volume and low cost, and the requirements of non-volatility, high density, and low cost are primary driving factors in the design of memory devices. Low power consumption is also desirable because smaller power sources can be used, reducing the size of consumer electronic products.
Nonvolatile memory devices typically have one time programmable (OTP) or re-programmable memory cells. A re-programmable memory cell can be switched among binary states. An OTP memory cell""s state is permanent once the cell is programmed. OTP memory devices can generally be classified as one of fuse, anti-fuse, charge storage, or mask read only memory (mask ROM).
A fuse memory cell is programmed by applying a large voltage across the cell so that the cell is xe2x80x9cblownxe2x80x9d during programming. The binary state of fuse memory cells can be detected as the resistance across the cell measured during a read process. Fuse memory devices are unpopular because of the large current required to program fuse memory cells. The large programming current requires a high voltage power supply having large drive transistors, or a charge pump circuit. Fuse memory cells also occupy a large area of the substrate because of contact regions required for each fuse element. The large cell size decreases array density and increases the size of fuse memory devices.
Fuse memory cells often include an isolation element such as a diode or transistor, which further increases cell size. Isolation diodes and transistors used in fuse memory cells have limited current capability, and may be damaged by the large write currents required to program the memory cells. In addition, the isolation diodes and transistors are typically active silicon-based elements, which are most readily formed on a silicon crystal substrate. Isolation elements of this type preclude stacking of multiple layers of fuse OTP arrays, decreasing possible array density. Other silicon-based isolation elements such as micro-crystalline and amorphous diodes and transistors enable stacking, but increase complexity and cost of fabrication. Finally, fuse memory cells are characterized by a wide breakdown threshold distribution. A wide breakdown threshold distribution means a large variation in write current may be required to program a cell. The write current must typically be increased to account for the wide breakdown threshold distribution.
Conventional anti-fuse memory cells typically include a metal-dielectric-metal stack. Conventional anti-fuse memory cells are programmed by applying a large write potential across the cells. The write potential triggers the anti-fuse and reduces the resistance across a programmed memory cell. Conventional anti-fuse memory cells suffer many of the same disadvantages as fuse/transistor cells. For example, conventional anti-fuse memory cells require a large write potential, and may require active silicon-based isolation elements.
A common charge storage memory is EPROM. EPROM memory utilizes Fowler-Nordheim tunneling to transfer charge from a substrate to a floating gate in the memory cell. EPROM memories require a large write voltage, and the write speed in EPROM devices is limited by tunneling current density.
Mask ROM memories are programmed at the time of fabrication, rather than at the user level (xe2x80x9cfield programmingxe2x80x9d). Therefore, each batch of mask ROM devices is application-specific. As in most manufacturing processes, cost savings are realized with increased volume. Therefore, in order for mask ROM production to be cost-effective, there must be a large demand for an application-specific memory. The requirement for large-scale processing renders mask ROM too costly for many applications.
A need therefore exists for a low cost memory device having memory cells capable of high density arrangement. A need also exists for a memory device capable of high speed processing and that does not require excessive processing power.
According to a first aspect, a memory device includes dual tunnel junction memory cells having a first tunnel junction and a second tunnel junction in series with the first tunnel junction. The first tunnel junction may be changed from a first resistance state to a second resistance state. The memory cells are the data storage elements for the memory device, and the two resistance states represent binary states of the memory cells. The first and second tunnel junctions have differing anti-fuse characteristics, and the memory cells can be programmed so that the first tunnel junction is shorted while the second tunnel junction resistance remains substantially unchanged.
According to the first aspect, if the first tunnel junction is shorted, the second tunnel junction provides an isolation function for the programmed memory cell. Therefore, active silicon-based isolation diodes and/or transistors are not required to isolate the memory cells in the memory device. The memory device can therefore include stacked memory elements, increasing array density.
Also according to the first aspect, the tunnel junction memory cells are smaller than conventional memory cells having diode/transistor isolation elements. This aspect further increases array density. The absence of diode/transistor isolation elements also simplifies the manufacture of the memory device.
According to a second aspect, a selected memory cell can be programmed by applying a write current to the memory cell. The resistance of the first tunnel junction can be higher than the resistance of the second tunnel junction, so that a higher voltage is created across the first tunnel junction when the write current is applied.
According to the second aspect, the higher voltage across the first tunnel junction can exceed a breakdown voltage of the first tunnel junction, and can be used to program the selected cell. The resistance of the first tunnel junction can be increased by reducing a tunneling area of the first tunnel junction, which advantageously reduces the possible area for defects in the dielectric. The reduction in possible defects reduces the voltage/current programming distribution (breakdown threshold distribution) of the memory device, which in turn reduces the power requirements for the memory device.
According to a third aspect of the invention, the dual tunnel junction memory cells can be programmed by applying a write voltage that exceeds a breakdown voltage of the first tunnel junction. The breakdown voltage of the first tunnel junction can be determined by the thickness of and the material used to form a dielectric in the first tunnel junction.
According to the third aspect, the programming voltage of the tunnel junction can be reduced by reducing the breakdown voltage of the dielectric layer. The programming voltage can therefore be lower than in conventional anti-fuse devices. A low programming voltage allows for smaller, low power write circuitry in the memory device.
According to a fourth aspect, the breakdown threshold distribution of the first tunnel junction can be reduced by providing a dielectric for the first tunnel junction having nonuniform thickness. The nonuniform thickness can be established by forming a feature in the dielectric, where tunneling occurs at the feature during a write process.
According to the fourth aspect, the feature can be an area of reduced thickness in the dielectric, which reduces the breakdown voltage of the first tunnel junction. The feature also provides a relatively small tunneling area for the first tunnel junction, reducing the breakdown threshold distribution of the memory device.
Other aspects and advantages will become apparent from the following detailed description, taken in conjunction with the accompanying drawings.